1. Field of the Invention
The present invention relates to a vector computer based on vector processing performed by a pipeline method.
2. Description of the Related Art
An operation of repeatedly performing the same operation for vector data regularly stored in a memory is called a vector operation. In Fortran, for example, a vector operation of vectors A, B, and C as shown in FIG. 1A is performed such that processing in which an operation is performed using B(I) and C(I) as operands and an operation result is substituted in destination A(I) is repeatedly performed while suffix I is sequentially changed by a DO loop.
A pipeline method is known as a method of increasing an operation speed of the vector operation. According to the pipeline method in which the number of stages of a pipeline is set to be three, an operation shown in FIG. 1A is performed as shown in FIG. 1B.
First, in cycle 1, addresses of B(1) and C(1) are set as read addresses, and an address of A(1) is set as a write address. Then, B(1) and C(1) are read out, and an operation of B(1)+C(1) is started at a given stage in the pipeline. In this case, assume that this operation requires two cycles.
In next cycle 2, although the operation started in cycle 1 is continuously executed, addresses of B(2) and C(2) are set as read addresses. Then, B(2) and C(2) are read out, and an operation of B(2)+C(2) is started in another stage in the pipeline. In this case, since an operation result of B(1)+C(1) is not obtained yet in cycle 2, the address of A(1) is still set as the write address.
In cycle 3, since result A(1) of the operation started in cycle 1 is obtained, this result is written at the given stage. At the same time, B(3) and C(3) are read out, and an operation of B(3)+C(3) is started in still another stage in the pipeline.
Similarly, in cycle i+2, result A(i) of an operation started in cycle i is obtained. Therefore, A(i) is written, and at the same time B(i+2) and C(i+2) are read out to perform an operation of B(i+2)+C(i+2). When an operation is repeatedly and continuously processed without waiting for a previous operation result as described above, this operation is called vector processing.
According to such vector processing, when two cycles are required for one operation as described above, first operation result A(1) is obtained with a delay of two cycles. However, after the first operation result, an operation result can be advantageously obtained for each cycle.
A recursive operation in which a vector of an operand (A(I)) is the same as that of destination (A(I+3)) as shown in FIG. 2A will be described. Assume that a difference (in this case, three) between suffixes of vector A of the destination and vector A of the operand equals number n (=3) or more of stages of the pipeline. In this case, as shown in FIG. 2B, since result A(4) of an operation of A(1)+C(1) started in cycle 1 is obtained in cycle 2 and written in cycle 3, A(4) can be read out (referred to) in cycle 4. Therefore, such a recursive operation can be vectorially processed.
In a recursive operation, assume that a difference (in this case, one) between suffixes of vector A of the destination and that A of the operand is less than number n (=3) of stages of the pipeline as shown in FIG. 3A. In this case, since operation result A(2) of A(1)+C(1) started in cycle 1 is not obtained yet in cycle 2, A(2) and C(2) cannot be referred to unless writing of this operation result is finished, i.e., cannot be referred to before cycle 4. Therefore, as shown in FIG. 3B, this operation cannot be continuously performed in each cycle, i.e., cannot be vectorially processed.
As described above, even if the pipeline system is adopted, in a recursive operation in which a difference between suffixes of vectors of a destination and an operand is less than number n of stages of a pipeline, vector processing cannot be performed.
Therefore, in order to perform a recursive operation, number n of stages of the pipeline may be stored in a compiler in advance to determine whether the difference between the suffixes is larger than number n of stages of the pipeline upon compiling, thereby determining in accordance with this determination result whether vector processing is performed in this operation. In this case, however, when the number of stages of the pipeline is increased, the compiler must be modified in accordance with a new pipeline stage number. In addition, when computers have the same architecture and only different numbers of stages of pipelines, a compiler corresponding to the number of stages of a pipeline of each computer must be provided, resulting in troublesome manufacture of compilers.
As shown in FIG. 4, when a suffix of a destination includes variable k, variable k is determined not in compiling but in execution. Therefore, even if k.gtoreq.n is obtained in execution, it is determined that vector processing is impossible upon compiling.
In a subroutine as shown in FIG. 5A, although a destination and an operand of statement number 10 are not apparently the same, when first and second arguments are accessed as the same argument at a call of a subroutine as shown in FIG. 5B, a problem of recursive data reference as described above is posed. This problem may be solved if the same variable is not assigned to the first and second arguments. However, in this case, generality of the subroutine is lost, and compatibility of the program is reduced.
For this reason, in conventional vector computers, vector processing is not performed at all in recursive operations although it can be performed in some operations. As a result, an operation speed is reduced to a fraction of several tens of that obtained when vector processing is performed.